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12.4
AC Characteristics
Symbol
Parameter
Min
Max
Units
f SCK
f RDLF
t SCKH
t SCKL
Serial Clock (SCK) Frequency
SCK Frequency for Read Array (Low Frequency - 03h opcode)
SCK High Time
SCK Low Time
6.4
6.4
70
33
MHz
MHz
ns
ns
t SCKR
(1)
SCK Rise Time, Peak-to-Peak (Slew Rate)
0.1
V/ns
t SCKF (1)
t CSH
t CSLS
t CSLH
t CSHS
t CSHH
t DS
t DH
t DIS (1)
t V (2)
t OH
t HLS
t HLH
t HHS
t HHH
t HLQZ (1)
t HHQX (1)
t WPS (1)(3)
SCK Fall Time, Peak-to-Peak (Slew Rate)
Chip Select High Time
Chip Select Low Setup Time (relative to SCK)
Chip Select Low Hold Time (relative to SCK)
Chip Select High Setup Time (relative to SCK)
Chip Select High Hold Time (relative to SCK)
Data In Setup Time
Data In Hold Time
Output Disable Time
Output Valid Time
Output Hold Time
HOLD Low Setup Time (relative to SCK)
HOLD Low Hold Time (relative to SCK)
HOLD High Setup Time (relative to SCK)
HOLD High Hold Time (relative to SCK)
HOLD Low to Output High-Z
HOLD High to Output Low-Z
Write Protect Setup Time
0.1
50
5
5
5
5
2
3
0
5
5
5
5
20
6
6
6
6
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t WPH
(1)(3)
Write Protect Hold Time
100
ns
t SECP (1)
t SECUP (1)
Sector Protect Time (from Chip Select High)
Sector Unprotect Time (from Chip Select High)
20
20
ns
ns
t EDPD
(1)
Chip Select High to Deep Power-down
3
μs
t RDPD (1)
Notes:
Chip Select High to Standby Mode
1. Not 100% tested (value guaranteed by design and characterization).
3
μs
2. 15 pF load at 70 MHz, 30 pF load at 66 MHz.
3. Only applicable as a constraint for the Write Status Register command when SPRL = 1
32
AT26DF081A
3600G–DFLASH–06/09
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